Careers
The ideal candidates should master the entire backend flow design from RTL to GDSII including synthesis, Formal Verification, Floor-planning, PnR, STA, and Physical Verification (DRC / LVS).
Management positions are open as well.
Qualification, skills and knowledge requirements:
Physical Design Engineers
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B.Sc. in Electrical Engineering (Electronics) / Physics / Computer Engineering - must
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At least 3 years experience in backend design of SoC - must
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Experience with place & route tools and flows (Synopsys / Cadence) - must
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Understanding of DRC and LVS – must
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Know-how in floor-planning, power grid distribution and analysis – advantage
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Experience with integration of mixed-signal IPs and I/O integration – advantage
Circuit or Mixed Signal Design Engineers
The ideal candidates should have hands-on experience in circuit design of FinFET technology nodes.
Management positions are open as well.
Qualification, skills and knowledge requirements:
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B.Sc. in Electrical Engineering / Physics / Computer Engineering - must
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At least 3 years of experience - must
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Experience in circuits and\or mixed-signal design and simulations – must
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Familiarity with advanced nodes (16nm, 7nm, 5nm) – advantage
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Characterization and integration of analog IP blocks into custom digital blocks - Advantage
Frontend Design Engineers
The ideal candidates should have hands-on experience in RTL implementation and verification.
Management positions are open as well.
Qualification, skills and knowledge requirements:
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B.Sc. in Electrical Engineering / Physics / Computer Engineering - must
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At least 3 years of hands-on experience - must
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Experience in RTL implementation of high-speed low-power designs
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Experience in VLSI development using Verilog or SystemVerilog, and with design verification, synthesis, timing/power analysis, and DFT – must
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Knowledge in modern high-performance CPU architecture and micro-architecture – advantage