Technology
Our technology
For the past 50 years, the semiconductor industry has traditionally pursued scaling down the size of transistors to deliver consecutive price-performance improvements. However, there is a different path to achieve price-performance improvement; that is, by reducing the complexity of digital circuits, as well as introducing novel optimization techniques to the design flow, that result in SOTA-superior power-efficient processors.
CMOS+
CMOS+ is a novel chip design technology that comprises RTL optimization, logic synthesis optimization, new, proprietary standard cells, and more. It is fully compatible with conventional CMOS fabrication, as well as the common EDA tools. It is future-proof and delivers a PPA advantage independently of the CMOS technology node, as well as backward compatibility with mature CMOS technology nodes.