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Quasi-CMOS is a new VLSI design paradigm that delivers novel standard cells, a format that is very familiar to VLSI designers. The building blocks of VLSI design are novel VLSI blocks as well as full cores that are fully compatible with CMOS, standard design and layout tools, and, most importantly, fully compatible with the CMOS manufacturing process.
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https://medium.com/looltalk/neologic-why-we-invested-106c44a7e70
NeoLogic: Why We Invested
The semiconductor industry challenges
Artificial Intelligence (AI) and Machine Learning (ML) are enabling new applications such as smart devices, IoT, autonomous vehicles, and others. Many of these AI-powered applications require running on high-performance power-hungry processors. “Some predictions have stated that data center power consumption could grow by 2X to 7X without substantial innovation.” (Dermot O’Driscoll, ARM VP Product Infrastructure) [1] due to the increasing workload of AI and ML. In addition, area saving is challenging as transistors scale down has come to halt [2].
A new FinFET generation delivers a few percent improvements in PPA. In state-of-the-art FINFET technology a 20% PPA improvement is roughly equivalent to 3 technology generations as; Rod Metcalfe, product management group director in Cadence’s Digital & Signoff Group said: “Increase performance by 14%, improve leakage power by 7%, and density by 5%. This can be significant.”[3].
Decreasing PPA (Power, Performance, Area) improvement in advanced technology nodes
The Non-Recurrent Engineering (NRE) cost of microprocessors design is getting increasingly high when switching to new technology.
Moreover, wafer cost dramatically increases the more advanced a technology node is which further contributes to increasing operations costs for both fabless and IDM companies.
Exponentially rising costs of advanced
technology nodes
Increased NRE cost
“The average cost of designing a 28nm chip is US$40 million,” said Handel Jones, CEO of International Business Strategy (IBS). “By comparison, the cost of designing a 7nm chip is $217M, and the cost of designing a 5nm device is $416M. 3nm design will cost up to $590M” [3].
Design complexity
Computation Efficiency
Processors' complexity is increasing to meet the applications' requirements. Today's designers struggle to meet the rising demand for computation power while meeting budgetary constraints of increased design NRE & fabrication costs in the face of long design cycle time.
The number of IP blocks in complex SoC designs today may exceed 100+. The SoC\ASIC's one-size-fits-all approach is no longer viable which drives the industry towards hardware accelerators on one side and ASIPs on the other and opens the door for a multitude of approaches to deliver more efficient computing.
Currently, there is no known new technology that can further maintain the semiconductors industry’s historical price- performance improvement with each new generation. As transistors reached the 10nm node (~ 40 Si atoms) it is clear that no physical shrinkage of gate dimensions is possible any further.
[1] https://semiengineering.com/why-data-center-power-will-never-come-down/?cmid=1fcad65e-6f26-4f9a-9899-56dc618e547c
[2] https://www.cnet.com/news/moores-law-is-dead-nvidias-ceo-jensen-huang-says-at-ces-2019/
[3] https://semiengineering.com/improving-ppa-in-complex-designs-using-ai/?cmid=b908c1e0-3c7b-4ef2-adad-8780454dc665
TSMC has developed its 3nm process node and is expected to introduce a 2nm process node by 2025. In China, SMIC began producing 14nm chips back in 2019and is still lagging. Intel is following in the footsteps of TSMC but other companies have given up. NeoLogic technology can leapfrog up to 3 generations ahead in any process node. Our unique value proposition is particularly noticeable in sub 40nm technology nodes, where production and development costs are rising exponentially. For example, the development of a processor at 16nm using Quasi-CMOS technology is expected to deliver a PPA equivalent (design-dependent) of 10nm or 7nm without paying the high costs, cycle time as well as lower yield of the more advanced node.