Careers
The ideal candidates should have knowledge of the full ASIC
backend flow from RTL to GDS including synthesis, Formal Verification, Floor-planning, PnR, STA and Physical Verification (DRC / LVS).
Qualification, skills and knowledge requirements:
Physical Design Engineers
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B.Sc. in Electrical Engineering (Electronics) / Computer Engineering - must
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3+ years experience in backend design of SoC - must
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Experience with place & route tools and flows (Synopsys / Cadence) - must
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Understanding of DRC and LVS – must
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Know-how in floor-planning, power grid distribution and analysis – advantage
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Experience with integration of mixed-signal IPs and I/O integration – advantage
Analog and Mixed Signal Circuit Design Engineers
The ideal candidates should have solid hands-on experience in circuit design of FinFET technology nodes.
Qualification, skills and knowledge requirements:
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Experience in Analog and Mixed-Signal circuits design and simulations, targeting for the best PPA – must
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3-5 years of experience - must
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Experience designing circuits in advanced nodes (16nm, 7nm or 5nm) - must
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BSc or higher degree in Electrical or Computer Engineering – must
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Experience defining circuit floorplan, layout and integration requirements – advantage
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Characterization and integration of Analog IP blocks into custom digital blocks - Advantage
Frontend Design Engineers
The ideal candidates should have solid hands-on experience in RTL implementation and verification.
Qualification, skills and knowledge requirements:
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BSc in Electrical Engineering, Computer Science, or equivalent practical experience – must
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3-5 years of hands-on experience - must
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Experience in RTL implementation of high-speed low power designs – must
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Experience in VLSI development using Verilog or SystemVerilog, and with design verification, synthesis, timing/power analysis, and DFT – must
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Knowledge in modern high-performance CPU architecture and micro-architecture – advantage