The semiconductors industry has traditionally pursued technological improvement (transistor scale down) for delivering consecutive price-performance improvements. However, there is a different path to achieve price-performance improvement and that is by reducing the complexity of circuits (i.e., the complexity of transistors' realization of logic and sequential circuits). Quasi-CMOS integrates standard CMOS gates\cells with reduced complexity gates\cells to cut down the transistor count of digital circuits by up to 3x at any technology node. It enables a significant increase in the transistor packing density of our proprietary cores. Our technology is fully compatible with the CMOS fabrication processes (130nm - 2nm) as well as common EDA tools.
CMOS is a fan-in limited technology (up to 4 inputs). High fan-in CMOS circuits require a tree-topology that consumes area and power. We overcame this limitation with 6-32 inputs single stage-gates that reduce the critical path, area as well as power consumption.
Breaking the limits of CMOS technology:
Our single-stage (non-existing) gates and circuits affect the entire design flow from the gate level up to the logic synthesis. A processor synthesized with our technology is more compact (fewer instances) and has a shorter critical path.
A new infrastructure for processor design:
By reducing the die size (and improving yield in tandem), NeoMOS delivers a major cost saving for sub 40nm technology nodes where both NRE and wafer prices increase exponentially.
Up to 50% reduced power consumption.
Up to 40% reduced area.
On par or better latency.
PPA (with respect to std. CMOS):
• High fan-in single-stage logic gates (6-32 inputs and more)
• Power & area efficient DFF and registers
• Power efficient buffers (area trade-off)
• Efficient arithmetic as well as other blocks